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Std.Tactic.BVDecide.Bitblast.BVExpr.Circuit.Impl.Operations.Udiv

This module contains the implementation of a bitblaster for BitVec.udiv. The implemented circuit is a shift subtractor.

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def Std.Tactic.BVDecide.BVExpr.bitblast.blastUdiv.blastDivSubtractShift {α : Type} [Hashable α] [DecidableEq α] {w : Nat} (aig : Sat.AIG α) (falseRef trueRef : aig.Ref) (n d : aig.RefVec w) (wn wr : Nat) (q r : aig.RefVec w) :
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theorem Std.Tactic.BVDecide.BVExpr.bitblast.blastUdiv.blastDivSubtractShift_le_size {α : Type} [Hashable α] [DecidableEq α] {w : Nat} (aig : Sat.AIG α) (falseRef trueRef : aig.Ref) (n d : aig.RefVec w) (wn wr : Nat) (q r : aig.RefVec w) :
aig.decls.size (blastDivSubtractShift aig falseRef trueRef n d wn wr q r).aig.decls.size
theorem Std.Tactic.BVDecide.BVExpr.bitblast.blastUdiv.blastDivSubtractShift_decl_eq {α : Type} [Hashable α] [DecidableEq α] {w : Nat} (aig : Sat.AIG α) (falseRef trueRef : aig.Ref) (n d : aig.RefVec w) (wn wr : Nat) (q r : aig.RefVec w) (idx : Nat) (h1 : idx < aig.decls.size) (h2 : idx < (blastDivSubtractShift aig falseRef trueRef n d wn wr q r).aig.decls.size) :
(blastDivSubtractShift aig falseRef trueRef n d wn wr q r).aig.decls[idx] = aig.decls[idx]
def Std.Tactic.BVDecide.BVExpr.bitblast.blastUdiv.go {α : Type} [Hashable α] [DecidableEq α] {w : Nat} (aig : Sat.AIG α) (curr : Nat) (falseRef trueRef : aig.Ref) (n d : aig.RefVec w) (wn wr : Nat) (q r : aig.RefVec w) :
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@[irreducible]
theorem Std.Tactic.BVDecide.BVExpr.bitblast.blastUdiv.go_le_size {α : Type} [Hashable α] [DecidableEq α] {w : Nat} (aig : Sat.AIG α) (curr : Nat) (falseRef trueRef : aig.Ref) (n d : aig.RefVec w) (wn wr : Nat) (q r : aig.RefVec w) :
aig.decls.size (go aig curr falseRef trueRef n d wn wr q r).aig.decls.size
@[irreducible]
theorem Std.Tactic.BVDecide.BVExpr.bitblast.blastUdiv.go_decl_eq {α : Type} [Hashable α] [DecidableEq α] {w : Nat} (aig : Sat.AIG α) (curr : Nat) (falseRef trueRef : aig.Ref) (n d : aig.RefVec w) (wn wr : Nat) (q r : aig.RefVec w) (idx : Nat) (h1 : idx < aig.decls.size) (h2 : idx < (go aig curr falseRef trueRef n d wn wr q r).aig.decls.size) :
(go aig curr falseRef trueRef n d wn wr q r).aig.decls[idx] = aig.decls[idx]
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